Evaluating the performance of devices in representative “benchmark” circuits is a well-established engineering practice in the semiconductor industry. However, NRI and STARnet are the first research programs to develop a comparable methodology for evaluating the relative capabilities of emerging devices which operate by a variety of principles that are fundamentally different from those that govern the operation of the established silicon field-effect transistor technology.
In recent years, NRI-STARnet benchmarking has enabled concise communication of research outcomes, focused researcher’s attention on key technical challenges, and sparked invention. This research involves the INDEX, CNFD, and SWAN Centers from NRI combining efforts with FAME, LEAST, and C-SPIN Centers from STARnet.
The focus is to maintain and improve the established benchmarking methodology, evaluating the potential performance of the various NRI and STARnet devices in the established benchmark circuits, and incorporating additional device concepts as they emerge through ongoing research.
Prof. Naeemi will take benchmarking of emerging devices to a new level of sophistication. He and his team will benchmark emerging device concepts for application in memory arrays. They will explore and quantify the value of non-volatility, an attribute of certain emerging devices for logic. They will develop and quantify metrics for device-to-device connections. Perhaps most challenging, Prof. Naeemi will lead development of a rigorous benchmarking methodology for non-Boolean (analog) computational circuits being explored for future applications such as artificial neural networks.
A more comprehensive assessment with uniform engineering assumptions for all devices, led by Dmitri Nikonov and Ian Young of Intel.
D.E. Nikonov and I.A. Young, "Uniform Methodology for Benchmarking Beyond-CMOS Logic Devices," IEEE IEDM, pp. 573-576, Dec. 2012;
D.E. Nikonov and I.A. Young,"Overview of Beyond-CMOS Devices and a Uniform Methodology for Their Benchmarking," Proc. IEEE, vol. 101, no. 12, pp. 2498-2533, Dec. 2013.
The extension of the methodology to devices pursued by three new NRI centers (CNFD, SWAN, INDEX) and three new STARnet centers (C-SPIN, FAME, LEAST) was completed in 2014.
D.E. Nikonov and I.A. Young, "Benchmarking of Beyond-CMOS Exploratory Devices for Logic Integrated Circuits," IEEE J. Exploratory Sold-State Computational Devices and Circuits, vol. 1, pp. 3-11, July 2015.
A major extension of the benchmarking methodology for non-Boolean computing platform based on the cellular neural network, led by Prof. Azad Naeemi at Georgia Tech.
C. Pan and A. Naeemi, “Non-Boolean Computing Benchmarking for beyond-CMOS Devices based on Cellular Neural Network,” IEEE Journal of Exploratory Solid-State Computational Devices and Circuits (JxCDC), Dec., 2016.
An expanded benchmarking based on Boolean and non-Boolean computing platforms for devices pursued by three NRI centers (CNFD, SWAN, INDEX) and three STARnet centers (C-SPIN, FAME, LEAST) was completed in Dec. 2017.
C. Pan and A. Naeemi, “An Expanded Benchmarking of Beyond-CMOS Devices Based on Boolean and Neuromorphic Representative Circuits,” IEEE Journal of Exploratory Solid-State Computational Devices and Circuits (JxCDC), Jan., 2018.
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