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GRC Science Area
CADTS – Computer Aided Design & Test Sciences
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- 1:
Integrated Circuit Having Clock-Line Control and Method for Testing...
- Integrated Circuit Having Clock-Line Control and Method for Testing Same Application Type: Utility Patent Number: 5519713 Country: United States Status: Filed on 2-Dec-1993, Issued ...
URL: https://www.src.org/library/patent/p0022/
Modified: 1996-05-21 - 21KB
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- 2:
 Final Report - Workshop on Failure and Uncertainty in Mixed-Signal...
- National Science Foundation Workshop on Failure and Uncertainty in Mixed-Signal Circuits and Systems Arlington, Virginia July 8-9, 2010 Principal Investigators: Ralph Cavin, ...
URL: https://www.src.org/calendar/e004025/final-report.pdf
Modified: 2011-06-01 - 914KB
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- 3:
TECHCON 2012 (Event E004114) - SRC
- TECHCON 2012 Date: Monday, Sept. 10, 2012, 8 a.m. - Tuesday, Sept. 11, 2012, 10 p.m. CT Location: Renaissance Austin Hotel, Austin, TX, United States Event ID: E004114 E004114 ...
URL: https://www.src.org/calendar/e004114/
Modified: 2013-03-11 - 98KB
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- 4:
Systems and Methods for Testing Integrated Circuits (Patent P0342...
- Systems and Methods for Testing Integrated Circuits Application Type: Utility Patent Number: 7032151 Country: United States Status: Filed on 13-Nov-2002, Issued on 18-Apr-2006, ...
URL: https://www.src.org/library/patent/p0342/
Modified: 2006-04-18 - 22KB
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- 5:
Multi-Layer Integrated Circuits Having Isolation Cells for Layer...
- Multi-Layer Integrated Circuits Having Isolation Cells for Layer Testing and Related Methods Application Type: Continuation (in part) Patent Number: 10838003 Country: United States ...
URL: https://www.src.org/library/patent/p1826/
Modified: 2020-11-17 - 25KB
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- 6:
Multi-Layer Integrated Circuits Having Isolation Cells for Layer...
- Multi-Layer Integrated Circuits Having Isolation Cells for Layer Testing and Related Methods Application Type: Utility Patent Number: 10338133 Country: United States Status: Filed ...
URL: https://www.src.org/library/patent/p1639/
Modified: 2019-07-02 - 25KB
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- 7:
Method and System for Performing Global Routing on an Integrated...
- Method and System for Performing Global Routing on an Integrated Circuit Design Application Type: Utility Patent Number: 7661085 Country: United States Status: Filed on ...
URL: https://www.src.org/library/patent/p1032/
Modified: 2010-02-09 - 22KB
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- 8:
Method for Testing Analog and Mixed-Signal Circuits Using Functionally...
- Method for Testing Analog and Mixed-Signal Circuits Using Functionally Related Excitations and Functionally Related Measurements Application Type: Utility Patent Number: 7129734 ...
URL: https://www.src.org/library/patent/p0458/
Modified: 2006-10-31 - 25KB
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- 9:
Method for Testing Analog and Mixed-Signal Circuits Using Dynamic...
- Method for Testing Analog and Mixed-Signal Circuits Using Dynamic Element Matching for Source Linearization Application Type: Utility Patent Number: 7587647 Country: United States ...
URL: https://www.src.org/library/patent/p0468/
Modified: 2009-09-08 - 23KB
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- 10:
Methods for Characterizing, Generating Test Sequences for, and...
- Methods for Characterizing, Generating Test Sequences for, and Simulating Integrated Circuit Faults Using Fault Tuples and Related Systems and Computer Program Products Application ...
URL: https://www.src.org/library/patent/p0228/
Modified: 2004-12-28 - 22KB
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- 11:
E003932 - Variability Forum - Nowka
- Test Structures for Variability Characterization Kevin Nowka IBM Research - Austin nowka@us.ibm.com IBM Research Worldwide Watson Almaden Zurich Beijing Haifa Austin Tokyo Delhi ...
URL: https://www.src.org/calendar/e003932/e003932_s1_3_nowka.pdf
Modified: 2010-06-29 - 1.4MB
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- 12:
Testing Monolithic Three Dimensional Integrated Circuits (Patent...
- Testing Monolithic Three Dimensional Integrated Circuits Application Type: Utility Patent Number: 10775429 Country: United States Status: Filed on 2-Nov-2017, Issued on 15-Sep-2020 ...
URL: https://www.src.org/library/patent/p1746/
Modified: 2020-09-15 - 25KB
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- 13:
Built-in Current Testing of Integrated Circuits (Patent P0109...
- Built-in Current Testing of Integrated Circuits Application Type: Utility Patent Number: 5025344 Country: United States Status: Filed on 22-Feb-1990, Issued on 18-Jun-1991, Patent ...
URL: https://www.src.org/library/patent/p0109/
Modified: 1991-06-18 - 22KB
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- 14:
Method for Diagnosing Bridging Faults in Integrated Circuits...
- Method for Diagnosing Bridging Faults in Integrated Circuits Application Type: Utility Patent Number: 6202181 Country: United States Status: Filed on 3-Nov-1997, Issued on ...
URL: https://www.src.org/library/patent/p0199/
Modified: 2001-03-13 - 23KB
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- 15:
Method for Diagnosing Bridging Faults in Integrated Circuits...
- Method for Diagnosing Bridging Faults in Integrated Circuits Application Type: Continuation (in part) Patent Number: 6560736 Country: United States Status: Filed on 10-Jan-2001, ...
URL: https://www.src.org/library/patent/p0338/
Modified: 2003-05-06 - 23KB
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- 16:
Method and Architecture for Pre-bond Probing of TSVs in 3D Stacked...
- Method and Architecture for Pre-bond Probing of TSVs in 3D Stacked Integrated Circuits Application Type: Utility Patent Number: 8775108 Country: United States Status: Filed on ...
URL: https://www.src.org/library/patent/p1291/
Modified: 2014-07-08 - 22KB
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- 17:
System and Method to Test Integrated Circuits on a Wafer (Patent...
- System and Method to Test Integrated Circuits on a Wafer Application Type: Utility Patent Number: 7325180 Country: United States Status: Filed on 26-Nov-2003, Issued on ...
URL: https://www.src.org/library/patent/p0413/
Modified: 2008-01-29 - 22KB
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- 18:
Method and System for Synthesizing Relative Timing Constraints...
- Method and System for Synthesizing Relative Timing Constraints on an Integrated Circuit Design to Facilitate Timing Verification Application Type: Continuation Patent Number: ...
URL: https://www.src.org/library/patent/p1354/
Modified: 2012-11-27 - 24KB
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- 19:
Method and System for Synthesizing Relative Timing Constraints...
- Method and System for Synthesizing Relative Timing Constraints on an Integrated Circuit Design to Facilitate Timing Verification Application Type: Utility Patent Number: 8239796 ...
URL: https://www.src.org/library/patent/p1202/
Modified: 2012-08-07 - 24KB
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- 20:
Method and System for Testing an Electric Circuit (Patent P1260...
- Method and System for Testing an Electric Circuit Application Type: Utility Patent Number: 8742777 Country: United States Status: Filed on 29-Dec-2010, Issued on 3-Jun-2014, Patent ...
URL: https://www.src.org/library/patent/p1260/
Modified: 2014-06-03 - 22KB
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- 21:
Method of placing source contacts for efficient EDS\EOS protection...
- Method of placing source contacts for efficient EDS\EOS protection in grounded substrate MOS integrated circuit Application Type: Divisional Patent Number: 5468667 Country: United ...
URL: https://www.src.org/library/patent/p0373/
Modified: 1995-11-21 - 22KB
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- 22:
Power Switch Design and Method for Reducing Leakage Power in...
- Power Switch Design and Method for Reducing Leakage Power in Low-Power Integrated Circuits Application Type: Utility Patent Number: 8373493 Country: United States Status: Filed on ...
URL: https://www.src.org/library/patent/p1239/
Modified: 2013-02-12 - 22KB
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- 23:
Methods, Apparatus and Computer Program products for Synthesizing...
- Methods, Apparatus and Computer Program products for Synthesizing Integrated Circuits with Electrostatic Discharge Capability and Correcting Ground Rule Faults Therein Application ...
URL: https://www.src.org/library/patent/p0049/
Modified: 1998-08-18 - 27KB
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- 24:
Integrated Logic Circuit Including Impedance Fault Detection...
- Integrated Logic Circuit Including Impedance Fault Detection Application Type: Utility Patent Number: 5383194 Country: United States Status: Filed on 6-Nov-1992, Issued on ...
URL: https://www.src.org/library/patent/p0066/
Modified: 1995-01-17 - 21KB
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- 25:
Method and Apparatus For Rapidly Modeling and Simulating Intra...
- Method and Apparatus For Rapidly Modeling and Simulating Intra-Die Statistical Variations in Integrated Circuits using Compressed Parameter Models Application Type: Utility Patent ...
URL: https://www.src.org/library/patent/p1160/
Modified: 2012-10-16 - 24KB
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- 26:
Method and Apparatus for Simulating a Microelectric Interconnect...
- Method and Apparatus for Simulating a Microelectric Interconnect Circuit Application Type: Utility Patent Number: 5379231 Country: United States Status: Filed on 29-May-1992, ...
URL: https://www.src.org/library/patent/p0046/
Modified: 1995-01-03 - 21KB
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- 27:
PowerPoint Presentation
- RTI International High Performance Processing Systems Enabled by 3D Integration Bob Conn May 5, 2011 1 Bob Conn, RTI International, rconn@rti.org, bobconn@ieee.org RTI ...
URL: https://www.src.org/calendar/e004357/03-conn.pdf
Modified: 2011-05-04 - 1.1MB
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- 28:
TECHCON 2013 (Event E004683) - SRC
- TECHCON 2013 Date: Monday, Sept. 9, 2013, 8 a.m. - Tuesday, Sept. 10, 2013, 10 p.m. CT Location: Renaissance Austin Hotel, Austin, TX, United States Event ID: E004683 E004683 image ...
URL: https://www.src.org/calendar/e004683/
Modified: 2014-03-10 - 136KB
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- 29:
TECHCON 2011 (Event E004113) - SRC
- TECHCON 2011 Date: Monday, Sept. 12, 2011, 8 a.m. - Tuesday, Sept. 13, 2011, 10 p.m. CT Location: Renaissance Austin Hotel, Austin, TX, United States Event ID: E004113 E004113 ...
URL: https://www.src.org/calendar/e004113/
Modified: 2012-03-13 - 97KB
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- 30:
SRC/NSF Design Forum - Position Statement
- A Position Statement in the Forum on Future Directions for Design Automation Research Jason Cong UCLA Computer Science Department http://cadlab.cs.ucla.edu/~cong There are many ...
URL: https://www.src.org/...764/jason-cong-position-statement.pdf
Modified: 2011-08-02 - 35KB
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