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Steep-Slope Tunnel Field-Effect Transistor-Based Radio-Frequency Rectifier Design
Researchers at Pennsylvania State University have designed a III-V heterojunction tunnel field-effect transistor (HTFET)-based radio-frequency (RF) rectifier.
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Steep-Slope Tunnel Field-Effect Transistor-Based 6-bit Successive-Approximation-Register Analog-to-Digital Converter Design
The Pennsylvania State University research teams of Suman Datta and Vijay Narayanan have collaborated in the design of a III-V HTFET successive-approximation-register (SAR) analog-to-digital converter (ADC).
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IEEE Circuits and Systems Society Best Paper Award to Professor Kaushik Roy
IEEE Circuits and Systems Society VLSI Transactions awarded the 2013 Best Paper Award for the paper titled “Design Paradigm for Robust Spin-Torque Transfer Magnetic RAM (STT MRAM) From Circuit/Architecture Perspective” to Prof. Kaushik Roy, et al.
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Nitin Samarth Named a Fellow of the American Association for the Advancement of Science
Nitin Samarth, a Professor of Physics at Penn State University and the George A. and Margaret M. Downsbrough Head of the Department of Physics, has been named a Fellow of the American Association for the Advancement of Science (AAAS). Election as an AAAS Fellow is an honor bestowed by peers upon members of the AAAS, the world's largest general scientific society and the publisher of the journal Science.
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Professor Luca Carloni (Columbia) and Graduate Student Hung-Yi Liu’s Paper Named Best Paper for DATE13
Professor Luca Carloni (Columbia) and graduate student Hung-Yi Liu’s paper “Compositional System-level Design Exploration with Planning of High-level Synthesis” (Liu, Petracca, and Carloni) was given a Best Paper Award at the 2013 Design, Automation and Test in Europe Conference.
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Steep-Slope Devices: From Dark to Dim Silicon
While superior subthreshold characteristics of steep-slope devices can help to power up more cores, complementary metal–oxide–semiconductor technology to accelerate sequential applications as it reaches higher frequencies is still needed.
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Extending Nanoelectronics Research Initiative Device-Level Benchmarking to the Chip Level
Notre Dame researchers Mike Niemier and Sharon Hu have begun architectural-level benchmarking using data from Nanoelectronics Research Initiative benchmarking efforts to project how low-voltage steep-slope devices could ultimately impact the performance of a parallel benchmark suite (PARSEC) obtained by core scaling. For this work, they also leverage architectural models developed by Sankaralingam (University of Wisconsin) and Burger (Microsoft Research) that consider how technology, processor core design, and application models can impact core scaling.
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Tunnel Field-Effect Transistor-Based Cellular Neural Network Cell Design for Reduced Area and Power
A cellular neural network (CNN) is an analog architecture that can significantly improve both the power and performance of various information processing functions (e.g., pattern recognition, motion detection, etc.) can be particularly efficient when compared to functional equivalents that are executed on a more traditional microprocessor.
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David Blaauw and Dennis Sylvester Named Top Authors by ISSCC
David Blaauw and Dennis Sylvester have been named two of the top contributing authors to the International Solid-State Circuits Conference (ISSCC), which is the flagship conference of the Solid-State Circuits Society.
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Sharad Malik Co-Authors Paper Selected in Significant Contributions from 20 Years of the International IEEE Symposium on Field-Programmable Custom Computing Machines (1993-2013)
Sharad Malik co-authored a paper, “Accelerating Boolean Satisfiability with Configurable Hardware” which was selected for inclusion in “Significant Contributions from 20 Years of the International IEEE Symposium on Field-Programmable Custom Computing Machines (1993-2013).”
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Sharad Malik Received Three Awards from the 2013 Design Automation Conference
Sharad Malik received three awards from the 2013 Design Automation Conference.
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Naveen Verma Receives 2013 Intel Early Career Faculty Honor Program Award
Naveen Verma received the 2013 Intel Early Career Faculty Honor Program (ECFHP) Award and will be honored at a ceremony on June 26, 2013.
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NSF and SRC to Fund Research to Create Failure-Resistant Systems and Circuits for Tomorrow’s Computing Applications
$6 Million will support 29 researchers at 18 U.S. universities
SRC In The News
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Power saving on/off clock generator circuit achieves low jitter, fast locking, and near zero off-state power.
ICSS Featured Publication: Report on the Complete Circuit Design and Chip Layout of the Optimized Clock Generator
Featured Publication
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New global placement technique produces best results on more benchmarks than any other placer.
CADTS Featured Publication: Mathematical Optimization Techniques for Large-Scale Global Placement
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