ASCENT focuses on demonstration of foundational material synthesis routes and device technologies, novel heterogeneous integration (package and monolithic) schemes to support the next era of “functional hyper-scaling”. ASCENT features a cross-theme benchmarking effort led by center leadership to facilitate materials down-selection, validate projected device metrics with experiments and quantify system level energy-performance cost-form factor metric for intended application. The mission of ASCENT is to transcend the current limitations of high-performance transistors confined to a single planar layer of integrated circuit by pioneering vertical monolithic integration of multiple interleaved layers of logic and memory (Theme 1), by demonstrating beyond CMOS device concepts that combine processing and memory functions (Theme 2), by heterogeneously integrating functionally diverse nano-components into integrated microsystems (Theme 3), and by demonstrating in-memory compute kernels to accelerate future data intensive at-scale cognitive workloads (Theme 4).
Annual Report
- Year 4 Annual Report (Jan 1 - Dec 31, 2021)
- Year 3 Annual Report (Jan 1 - Dec 31, 2020)
- Year 2 Annual Report (Jan 1 - Dec 31, 2019)
- Year 1 Annual Report (Jan 1 - Dec 31, 2018)
Theme 3 Workshop
- Power Delivery - Version 1, 6/20
Contacts: Madhavan Swaminathan (GA Tech), Arijit Raychowdhury (GA Tech), Umesh Mishra (UCSB) - RF Heterogeneous Integration - Version 1, 6/20
Contacts: Madhavan Swaminathan (GA Tech), Patrick Fay (Notre Dame), Debdeep Jena (Cornell) - IO and Thermal Metrics - Version 1, 8/20
ASCENT Metrics
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This Year
1 Patent Applications1 Patents Granted -
Last Year
36 Research Data4 Patent Applications2 Patents Granted -
Since Inception
90 Projects17 Universities298 Research Scholars39 Faculty Researchers293 Liaisons2,391 Research Data1 Patent Applications9 Patents Granted