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ACE4S 21
ASCENT 21
CRISP 11
AMML 6
CBRIC 6
CONIX 5
GSRC 5
IMPACT 5
NEWLIMITS 5
ComSenTer 4
EBSM 4
LEAST 4
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C2S2 3
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DEEP3M 3
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Thrust/Theme
CD – Circuit Design 59
PAT – Patterning 36
TT – Test & Testability 32
SLD – System Level Design 23
AMS-CSD – Analog/Mixed-Signal Ci... 22
I3T – Innovative and Intelligent... 22
ISD – Integrated System Design 21
HWS – Hardware Security 20
Advanced Devices & Technologies 19
LPD – Logic & Physical Design 19
CADT – Computer-Aided Design and... 17
Factory Systems 17
NMP – Nanomanufacturing Material... 15
Pat(MPS) – Patterning 14
ASCENT-T1 – Vertical CMOS 12
NEM – Nanoengineered Materials 11
PKG – Packaging 10
CRISP-T1 – Hardware Support for ... 9
ASCENT-T2 – Beyond CMOS 8
BEP – Back End Processes 8
DCMOS – Digital CMOS Technologie... 8
Back End Processes 7
AMML-T1 – Antiferromagnetic Magn... 6
DesTech – Design Techniques 6
Doping Technologies 6
MT – Memory Technologies 6
CFM&TCM – CFM & Total Chemical M... 5
CONIX-T1 – ARENA Integrator 5
PatMat – Patterning Materials 5
VER – Verification 5
CBRIC-T2 – Neuromorphic Fabrics 4
ESH – Environment Safety and Hea... 4
IMPACT-T1 – Materials for Scaled... 4
Packaging & Interconnect Systems 4
Physical Design 4
ADA-T1 – Deft Development 3
AIHW – Artificial Intelligence H... 3
DEEP3M-T4 – Architectures 3
MTMP – Metrology Tools Matls & P... 3
Masks 3
TechCAD – Technology CAD 3
CBRIC-T1 – Neuro-inspired Algori... 2
CRISP-T3 – Scaling Applications ... 2
ComSenTer-T1 – Systems and Algor... 2
DesSyn – Design Synthesis 2
LMD – Logic and Memory Devices 2
Materials 2
Modeling & Simulation 2
NEWLIMITS-T2 – 2D Materials Devi... 2
SemiSynBio – Semiconductor Synth... 2
ADS – Alternative Device Structu... 1
AMS – Analog and Mixed-Signal De... 1
ASCENT-T4 – Merged Logic Memory ... 1
AdvTech – Advanced Technology 1
C&S – Controls and Sensing 1
CAPSL-T4 – Architectures and Sys... 1
CM – Compact Modeling 1
ComSenTer-T2 – mm-wave/THz ICs a... 1
ComSenTer-T3 – Application-speci... 1
DEEP3M-T2 – Circuits 1
DV – Design Verification 1
E2CDA2 – E2CDA 2.0 1
Front End Processes 1
IMPACT-T2 – Materials for Storag... 1
Multi-level Interconnect 1
NEWLIMITS-T1 – Novel Computing a... 1
NEWLIMITS-T3 – Advanced Manufact... 1
NEWLIMITS-T4 – Characterization ... 1
Processes – Processes 1
Reliability 1
SMART-T1 – Spin-orbit Torque Mat... 1
Synthesis & Verification 1
GRC Science Area
ICSS – Integrated Circuit & Syst... 88
MPS – Material & Process Science... 73
CADTS – Computer Aided Design & ... 70
NMS – Nanomanufacturing Sciences 69
LIT – Lithography Sciences 38
NIS – Nanostructure & Integratio... 34
DES – Design Sciences 29
DS – Device Sciences 24
IPS – Interconnect & Packaging S... 22
MBP – Materials & Bulk Processes... 22
MIC – Microstructure Sciences 18
PID – Process Integration & Devi... 18
INT – Interconnect Sciences 9
ES-H – Environmental Safety & He... 3
MFGPS – Manufacturing Process Sc... 3
FAC – Factory Sciences 1
1 through 30 of 478 similar documents, best matches first.   
Results by:Thunderstone Page: 1 2 3 4 5 6 7 8 9 10 next >>
1: Systems, Circuits and Computer Program Products Providing A Framework...
Systems, Circuits and Computer Program Products Providing A Framework for Secured Collaborative Training using Hyper-Dimensional Vector Based Data Encoding/Decoding and Related ...
URL: https://www.src.org/library/patent/p1927/
Modified: 2023-03-07 - 24KB
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2: Method, Circuits, and Articles of Manufacture for Searching within...
Method, Circuits, and Articles of Manufacture for Searching within a Genomic Reference Sequence for Queried Target Sequence using Hyper-Dimensional Computing Techniques Application ...
URL: https://www.src.org/library/patent/p1920/
Modified: 2021-07-14 - 22KB
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3: Method for in-SITU Dry Cleaning, Passivation, and Functionalization...
Method for in-SITU Dry Cleaning, Passivation, and Functionalization of GE Semiconductor Surfaces Application Type: Utility Patent Number: 9117653 Country: United States Status: ...
URL: https://www.src.org/library/patent/p1477/
Modified: 2015-08-25 - 25KB
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4: Switch-Linearized CMOS Track and Hold Circuit (Patent P0587)...
Switch-Linearized CMOS Track and Hold Circuit Application Type: Utility Patent Number: 7453291 Country: United States Status: Filed on 8-Sep-2005, Issued on 18-Nov-2008, Patent ...
URL: https://www.src.org/library/patent/p0587/
Modified: 2008-11-18 - 23KB
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5: Method for Cleaning, Passivation and Functionalization of SI...
Method for Cleaning, Passivation and Functionalization of SI-GE Semiconductor Sufraces Application Type: Divisional Patent Number: 10483097 Country: United States Status: Filed on ...
URL: https://www.src.org/library/patent/p1734/
Modified: 2019-11-19 - 25KB
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6: Method for In-Situ Dry Cleaning, Passivation, Functionalization...
Method for In-Situ Dry Cleaning, Passivation, Functionalization of SI-GE Semiconductor Surfaces Application Type: Utility Patent Number: 9818599 Country: United States Status: ...
URL: https://www.src.org/library/patent/p1429/
Modified: 2017-11-14 - 25KB
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7: Passivation of Silicon Dioxide Defects for Atomic Layer Deposition...
Passivation of Silicon Dioxide Defects for Atomic Layer Deposition Application Type: Utility Country: United States Status: Filed on 24-Apr-2020, Published by Patent Office ...
URL: https://www.src.org/library/patent/p1833/
Modified: 2020-04-24 - 23KB
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8: Method for Correcting a Mask Design Layout (Patent P1016) - SRC
Method for Correcting a Mask Design Layout Application Type: Continuation Patent Number: 7614032 Country: United States Status: Filed on 11-Dec-2006, Issued on 3-Nov-2009, Patent ...
URL: https://www.src.org/library/patent/p1016/
Modified: 2009-11-03 - 23KB
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9: Method for Correcting a Mask Design Layout (Patent P0386) - SRC
Method for Correcting a Mask Design Layout Application Type: Utility Patent Number: 7149999 Country: United States Status: Filed on 25-Feb-2004, Issued on 12-Dec-2006, Patent ...
URL: https://www.src.org/library/patent/p0386/
Modified: 2006-12-12 - 23KB
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10: Methods of Operating on Data in a Fully Homomorphic Encryption...
Methods of Operating on Data in a Fully Homomorphic Encryption System Using In-Situ Processing-in-Memory and Related Circuits Application Type: Utility Country: United States ...
URL: https://www.src.org/library/patent/p2112/
Modified: 2023-01-10 - 25KB
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11: Thermal ALD of Low Resistivity TiN Thin Film on Patterned Substrate...
Thermal ALD of Low Resistivity TiN Thin Film on Patterned Substrate Application Type: Utility Country: United States Status: Filed on 6-Dec-2022, Published by Patent Office ...
URL: https://www.src.org/library/patent/p2106/
Modified: 2022-12-06 - 23KB
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12: Interconnection Architecture and Method of Assessing Interconnection...
Interconnection Architecture and Method of Assessing Interconnection Architecture Application Type: Utility Patent Number: 7622779 Country: United States Status: Filed on ...
URL: https://www.src.org/library/patent/p1027/
Modified: 2009-11-24 - 23KB
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13: Low-Temperature Deposition of High-Quality Aluminum Nitride Films...
Low-Temperature Deposition of High-Quality Aluminum Nitride Films for Heat Spreading Applications Application Type: Utility Country: United States Status: Filed on 8-Feb-2021, ...
URL: https://www.src.org/library/patent/p1895/
Modified: 2021-02-08 - 29KB
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14: Method and Apparatus for Identifying Similar Regions of a Program...
Method and Apparatus for Identifying Similar Regions of a Program's Execution Application Type: Utility Patent Number: 7802236 Country: United States Status: Filed on 9-Sep-2003, ...
URL: https://www.src.org/library/patent/p0406/
Modified: 2010-09-21 - 22KB
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15: METHOD FOR CORRECTING A MASK DESIGN LAYOUT (Patent P1708) - SRC
METHOD FOR CORRECTING A MASK DESIGN LAYOUT Application Type: Utility Patent Number: 7149999 Country: United States Status: Filed on 25-Feb-2004, Issued on 12-Dec-2006, Patent ...
URL: https://www.src.org/library/patent/p1708/
Modified: 2006-12-12 - 23KB
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16: Method of Forming Low-Resistivity RU ALD Through a BI-Layer Process...
Method of Forming Low-Resistivity RU ALD Through a BI-Layer Process and Related Structures Application Type: Utility Country: United States Status: Filed on 6-Dec-2022, Published ...
URL: https://www.src.org/library/patent/p2099/
Modified: 2022-12-06 - 23KB
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17: Methods and Systems Configured to Specify Resources for Hyperdimension...
Methods and Systems Configured to Specify Resources for Hyperdimensional Computing Implemented in Programmable Devices using a Parameterized Template for Hyperdimensional Computing ...
URL: https://www.src.org/library/patent/p1966/
Modified: 2021-04-21 - 24KB
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18: Deposition of Aluminum Nitirde Templating Layers by Thermal Pulsed...
Deposition of Aluminum Nitirde Templating Layers by Thermal Pulsed Chemical Vapor Deposition for the Enhancement of Aluminum Nitride Thick Films Application Type: Utility Country: ...
URL: https://www.src.org/library/patent/p2129/
Modified: 2023-05-02 - 25KB
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19: Single-Mask Double-Patterning Lithography (Patent P1185) - SRC
Single-Mask Double-Patterning Lithography Application Type: Utility Patent Number: 8415089 Country: United States Status: Filed on 15-Mar-2010, Issued on 9-Apr-2013, Patent ...
URL: https://www.src.org/library/patent/p1185/
Modified: 2013-04-09 - 22KB
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20: Method and Apparatus for Designing Circuits Using High-Level...
Method and Apparatus for Designing Circuits Using High-Level Synthesis Application Type: Utility Patent Number: 7383529 Country: United States Status: Filed on 14-Feb-2005, Issued ...
URL: https://www.src.org/library/patent/p0529/
Modified: 2008-06-03 - 23KB
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21: Accuracy Configurable Adders and Methods (Patent P1359) - SRC
Accuracy Configurable Adders and Methods Application Type: Utility Patent Number: 9229686 Country: United States Status: Filed on 27-Aug-2012, Issued on 5-Jan-2016 Organization: ...
URL: https://www.src.org/library/patent/p1359/
Modified: 2016-01-05 - 24KB
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22: Non-Volatile Multi-Level Cell Memory using a Ferroelectric Superlattic...
Non-Volatile Multi-Level Cell Memory using a Ferroelectric Superlattice and Related Systems Application Type: Utility Patent Number: 11532355 Country: United States Status: Filed ...
URL: https://www.src.org/library/patent/p1942/
Modified: 2022-12-20 - 23KB
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23: Methods, Apparatus and Computer Program Products for Self-Calibrating...
Methods, Apparatus and Computer Program Products for Self-Calibrating Two-Dimensional Metrology Stages Application Type: Utility Patent Number: 5798947 Country: United States ...
URL: https://www.src.org/library/patent/p0017/
Modified: 1998-08-25 - 22KB
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24: Method for ALD Deposition on Inert Surfaces Via Al203 Nanoparticles...
Method for ALD Deposition on Inert Surfaces Via Al203 Nanoparticles Application Type: Utility Patent Number: 11127590 Country: United States Status: Filed on 5-Dec-2017, Issued on ...
URL: https://www.src.org/library/patent/p1750/
Modified: 2021-09-21 - 25KB
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25: Method and Apparatus for Detecting Lithographic Hotspots in a...
Method and Apparatus for Detecting Lithographic Hotspots in a Circuit Layout Application Type: Utility Patent Number: 7945870 Country: United States Status: Filed on 19-Mar-2007, ...
URL: https://www.src.org/library/patent/p0658/
Modified: 2011-05-17 - 21KB
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26: Low Temperature Atomic Layer Deposition of Oxides on Compound...
Low Temperature Atomic Layer Deposition of Oxides on Compound Semiconductors Application Type: Utility Patent Number: 10134585 Country: United States Status: Filed on 19-Aug-2015, ...
URL: https://www.src.org/library/patent/p1554/
Modified: 2018-11-20 - 22KB
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27: Energy Extraction (Patent P1465) - SRC
Energy Extraction Application Type: Utility Patent Number: 9369005 Country: United States Status: Filed on 3-Mar-2014, Issued on 14-Jun-2016, Patent Abandoned Organization: ...
URL: https://www.src.org/library/patent/p1465/
Modified: 2016-06-14 - 23KB
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28: Floorplan Evaluation, Global Routing, and Buffer Insertion for...
Floorplan Evaluation, Global Routing, and Buffer Insertion for Integrated Circuits Application Type: Utility Patent Number: 7062743 Country: United States Status: Filed on ...
URL: https://www.src.org/library/patent/p0405/
Modified: 2006-06-13 - 21KB
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29: Method for Passivating Surfaces, Functionalizing Inert Surfaces...
Method for Passivating Surfaces, Functionalizing Inert Surfaces, Layers and Devices Including Same Application Type: Utility Patent Number: 9761443 Country: United States Status: ...
URL: https://www.src.org/library/patent/p1445/
Modified: 2017-09-12 - 22KB
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30: Method, Apparatus and System for Designing an Integrated Circuit...
Method, Apparatus and System for Designing an Integrated Circuit Including Circuit Including Generating at Least One Auxiliary Pattern for Cell-Based Optical Proximity Correction ...
URL: https://www.src.org/library/patent/p1029/
Modified: 2011-01-18 - 22KB
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1 through 30 of 478 similar documents, best matches first.   
Results by:Thunderstone Page: 1 2 3 4 5 6 7 8 9 10 next >>