The Nanomanufacturing Materials and Processes (NMP) Program explores new materials and processes for scaled digital and analog device fabrication. Targeted research addresses critical challenges in patterning, nanoengineered materials, deposition and etch processes, process integration, metrology, and ESH (Environment, Safety, and Health). A very important additional role of NMP research is to educate students and strengthen the academic infrastructure in the aforementioned disciplines.
Environment, Safety and Health (ESH) Subprogram
The ESH subprogram supports an overall mission of enabling sustainability and environmentally benign processing in integrated-circuit manufacturing. The SRC Center for Environmentally Benign Semiconductor Manufacturing (EBSM) provides overall coordination and leveraged university/government support for our ESH research program, as well as an opportunity for additional teaming with companies and government agencies involved in ESH activities.
NMP has three research focus directions that include Patterning, Front-end Processes (FEP) and Back-end Processes (BEP).
This research focus includes research in the areas of imaging materials and pattern transfer, self-aligned patterning processes, alternative patterning techniques such as etch-free processing and directed self-assembly (DSA), and supportive metrology and modeling activities. The objectives of this subthrust are affordable, high-performance, and low-variability patterning options for advanced digital and analog/mixed-signal technologies.
Front-end Processes (FEP)
This research focus explores emerging research material and process options that address industry's strategic needs for active and passive device scaling, improvements in performance and reliability, and enhanced functionality.
Example topics include: (a) the chemistry and synthesis of materials which provide novel functionality and/or tunable properties, (b) material-enabled low-variability processes, (c) new thin-film deposition techniques for enhanced conformality, (d) the characterization and understanding of material interface effects, and (e) materials and processes enabling functional diversification on a CMOS platform and 3D heterogeneous integration.
Back-end Processes (BEP)
This subprogram addresses new directions for interconnects in the areas of Cu/low‑k extendibility, etch/deposition unit processes, reliability, novel global interconnect solutions, and radical new concepts for interconnect and the package/on-chip interconnect sub-system.
Example topics include: (a) new materials and processes to optimize Cu-based interconnect resistance and reliability, (b) new materials and processes to optimize low‑k dielectric capacitance and reliability, (c) optimization of interconnect interfaces and contacts, (d) alternate interconnect materials and concepts, and (e) back-end materials and processes enabling functional diversification of a CMOS platform.
Current28 Research Tasks22 Universities53 Students34 Faculty Researchers104 Liaison Personnel
This Year13 Task Starts25 Research Publications1 Patent Applications
Last Year12 Task Starts102 Research Publications2 Patent Applications1 Patents Granted
Since Inception92 Research Tasks53 Universities249 Students124 Faculty Researchers233 Liaison Personnel998 Research Publications10 Patent Applications2 Patents Granted