The Nanomanufacturing Materials and Processes (NMP) thrust explores new materials and processes for scaled digital and analog device fabrication. Targeted research addresses critical challenges in patterning, nanoengineered materials, deposition and etch processes, and metrology for future Front-End-of-Line (FEOL) and Back-End-of-Line (BEOL) manufacturing flows. A very important additional role of NMP research is to educate students and strengthen the academic infrastructure in the aforementioned disciplines.
In addition to the three major subthrusts listed below, the NMP thrust also includes embedded cross-cut research activities in common-need areas of metrology and novel analytic techniques, process modeling (including variability and defects), and design for manufacturing (DFM).
This subthrust includes research in the areas of imaging materials and pattern transfer, self-aligned patterning processes, alternative patterning techniques such as etch-free processing and directed self-assembly (DSA), and supportive metrology and modeling activities. The objectives of this subthrust are affordable, high-performance, and low-variability patterning options for advanced digital and analog/mixed-signal technologies.
Front-End Processes (FEP)
This subthrust explores emerging research material and process options that address industry's strategic needs for active and passive device scaling, improvements in performance and reliability, and enhanced functionality.
Example topics include: (a) the chemistry and synthesis of materials which provide novel functionality and/or tunable properties, (b) material-enabled low-variability processes, (c) new thin-film deposition techniques for enhanced conformality, (d) the characterization and understanding of material interface effects, and (e) materials and processes enabling functional diversification on a CMOS platform and 3D heterogeneous integration.
Back-end Processes (BEP)
This subthrust addresses new directions for interconnects in the areas of Cu/low‑k extendibility, etch/deposition unit processes, reliability, novel global interconnect solutions, and radical new concepts for interconnect and the package/on-chip interconnect sub-system.
Example topics include: (a) new materials and processes to optimize Cu-based interconnect resistance and reliability, (b) new materials and processes to optimize low‑k dielectric capacitance and reliability, (c) optimization of interconnect interfaces and contacts, (d) alternate interconnect materials and concepts, and (e) back-end materials and processes enabling functional diversification of a CMOS platform.
Current14 Research Tasks13 Universities30 Students24 Faculty Researchers48 Liaison Personnel
This Year3 Task Starts14 Research Publications2 Patent Applications
Last Year7 Task Starts124 Research Publications1 Patent Applications
Since Inception52 Research Tasks32 Universities144 Students68 Faculty Researchers135 Liaison Personnel610 Research Publications6 Patent Applications