SRC/NSF/A*STAR Forum on 2020 Semiconductor Memory Strategies: Processes, Devices and Architectures (by invitation only)

Forum Final Report:

SRC/NSF/A*STAR Forum on 2020 Semiconductor Memory Strategies: Processes, Devices, and Architectures

Panel I - Novel Memory Devices

Background: Memory devices include three integrated components: i) "storage node" (e.g. physics of memory operation), ii) "sensor" which reads the state (e.g. transistor), and iii) "selector" (e.g. transistor or diode), which allows a memory cell in an array to be addressed. Essential parameters of the memory element are: cell size/density, retention time, access time/speed and operating voltage/energy. None of existing baseline memory technologies, i.e. SRAM, DRAM and Flash perform well across all of these parameters, hence a memory hierarchy results for many information processing applications. If one could develop a "universal" memory element offering the best performance/density/persistence/cost attributes of DRAMs, SRAMs, and Flash, what would be the impact on the memory hierarchy? Are any of the emerging memory devices likely to achieve this degree of "universality"?

Discussion:

• Can an expanded application space for new memory devices be defined - Or will emerging memory devices simply be drop-in replacements for SRAM, DRAM and Flash?
• What are possible applications for "non-volatile" memory devices with retention times <10 y?
• Discuss potential of candidate devices for storage-class memory.
• What is the potential for scaling of different memory devices beyond the 22 nm ITRS node?
• What are the barriers for scaling of different memory devices beyond the 22 nm ITRS node?
• Can physics of operation suggest ways for reliability enhancement in new candidate devices?
• What are the pluses and minuses of 1T1R versus 1D1R structures at extreme scaling?
• What are the pluses and minuses of 1T1R versus 1D1R structures at extreme scaling?
• Are there physical phenomena that need to be explored for memory elements beyond the current electron movement, atomic movement, domain wall movement, electron correlation effects, and magnetic polarization approaches now being studied?
• Are there candidate technologies for analog memories? Applications?

Panel II - Materials for Future Memories

Background: New engineered materials play a critical role in the development of future memories. One of the important goals of materials research for memory technologies is a clear identification of the physical mechanism of memory operation. Next, an optimized materials system has to be synthesized, including e.g. precise control of composition, doping, defects etc. For a given memory technology, it is essential to optimize a "base" materials system. For example, resistance switching effects have been reported for many families of materials, and it is highly desirable to identify one or two optimal materials for practical implementations.

Reproducibility of results is serious problem with some emerging research materials. Also, stability of a material system with respect to endurance of the memory device is an important issue. Details of sample preparation, electrode materials, interfacial properties need to be thoroughly analyzed for addressing the endurance and reproducibility challenges.

For practical applications, synthesis of materials systems with optimized operational parameters should be achieved by taking into account the costs, which may also influence materials selection. For example organic/polymer materials are potential candidates for future memories, as they may offer lower-cost integration solutions.

Discussion:

• What are the key materials challenges for candidate emerging memory technologies?
• For each memory technology, what is the metrics for selection of an optimal material for practical implementation with respect of e.g. device performance, endurance, reproducibility, cost-effective synthesis etc.?
• Is it possible to derive a formula for an optimal material, e.g. A_xB_yC_z(:D) for a class of memory devices?
• What are criteria for the optimal material for "selecting device", e.g. diode?
• Are there new practically viable mechanisms for bi-stable switching, e.g. resonant tunneling, strong correlations etc.?
• What are the critical material properties that support the physical mechanism for the operation of emerging memory devices, e.g., electron-based memories, memories dependent on atom movement, memories utilizing domain wall movement, memories relying on electron correlation effects, or memories utilizing magnetic polarization.

Panel III - Memory Architectures

Background: Energy challenges in the memory system hierarchy include:

• Approximately 30% of power is consumed in support of memory hierarchy operation - there is a need to reduce the average energy consumed per memory access across the entire memory hierarchy.
• Processor scaling and the advent of multi-core architectures require significant increases in memory access bandwidth to minimize rapid growth in memory capacity

Operational reliability challenges include:

• Frequent check-pointing of the memory hierarchy to the hard drive is used to manage memory hierarchy failures
• Scaled memory devices may require a higher check-pointing frequency and hence consume more power.

The architectural tradeoffs between memory and logic structures could be impacted by the merger of memory elements with logic elements:

• As an example, combined memory and logic elements could be used to create energy-efficient look-up tables and programmable switch boxes
• Memory immersion with logic might provide for a level of check-pointing without the requirement to write to disk, thereby lowering energy use.

Discussion:

• How might emerging memory devices decrease memory hierarchy energy consumption by 10x while meeting performance requirements?
• What would be the impact of a "universal" logic/memory device on architectures?
• As we approach the limits of CMOS scaling, what makes more sense; eDRAM or eSRAM?
• What are applications for quasi-nonvolatile memory devices, e.g., devices having less than ten-year retention?
• How can the memory overhead circuits be reduced in complexity; especially for small arrays?
• What is the impact of emerging memory technologies on redefinition of the memory hierarchy?
  • New device physics for better memory characteristics?
  • Advanced integration technology such as 3D IC technology, etc.?
• Are there more efficient ways to quickly move massive amounts of data to/from chip, e.g. optical I/O, plasmonics etc.?
• Given current understanding on how brain works, is there a more optimal way to architect memory, e. g. for lower processing power?

Panel IV - Technological Platforms for Future Memories

Background: For embedded applications, the major challenge in integrating large memories with logic is the significant complexity it adds to the fabrication process. DRAM and Flash processes are still too complex to create an integrated SOC device. For stand-alone applications, cost per bit must go down dramatically for solid state disks to succeed rotating media. Is there a replacement memory technology on the horizon for DRAM?

The use of 3D IC with Through Silicon Vias (TSV) is very likely going to lead to dramatically different ways to build memories, including the low-power provisioning of high bandwidth and low latency.

Since the resultant memory geometry is usually very regular, there is potential for faster lithography scaling than for logic. Sub-22 nm lithography is more manageable for very regular structures, and this could be exploited, perhaps resulting in greater memory density.

Discussion:

• Discuss integration challenges of different memory devices for embedded applications
• Based on process integration, which candidate memory device has best potential for storage applications?
• Are their specific advantages or disadvantages of a given memory technology with respect to 3D integration?
• Are their specific advantages or disadvantages of a given memory technology with respect of extreme patterning solutions?
• Would non-optical patterning methods, such as nano-imprint and co-polymer based self-assembly impact architectural decisions?
  • e.g. larger arrays may be more cost-effective in extremely scaled systems
• What is the CMOS compatibility of the various proposed storage mechanisms for emerging memory, e.g., electron movement, atom movement, domain wall movement, electron correlation, magnetic polarization?

Panel V - Physical Limits of Memory Elements

Background: Desirable attributes of memory devices are high speed, high density, long retention, and low-voltage operation. However, the device physics sets fundamental limits and trade-offs on our ability to integrate all desirable attributes into one memory element. In particular, what can be called "The Voltage-Time Dilemma" appears to characterize the limits of electron-based memory scaling and performance: at the most basic level, for an arbitrary electron-charge based memory element, there is interdependence between operational voltage, the speed of operation and the retention time. More generally, cell dimensions are also part of the trade-off, hence the Space-Time-Energy compromise.

Memory devices include three integrated components: "storage node" (e.g. physics of memory operation), "sensor" which reads the state (e.g. transistor), and "selector" (e.g. transistor or diode), which allows a memory cell in an array to be addressed. Scaling limits for each of the three components need to be analyzed.

Discussion:

• What are scaling limits of the 'storage node' in new memory devices?
  • Which memory device offers optimum trade-off in resolving the voltage-time dilemma/space-time-energy compromise?
• What are scaling limits of selecting devices (e. g. diodes or transistors)?
• What is the impact of sensing devices on scalability?
• Based on device physics, can we identify new memory devices that are more tolerant to parameter variations?

Panel VI - Needs and Models for Collaborative Research

Background: There are many successful examples of collaborative research by semiconductor industry. What model would work best for the memory industry?

Discussion:

• Please identify drivers for research collaboration in emerging memory technologies
  • e.g. application landscape
• Please identify barriers to research collaboration in emerging memory technologies.
• What are promising areas for path-finding research in future memory technologies via an inter-regional industry-government-university collaboration?
• What principles should a collaborative model embrace?
  • How should the research be implemented?
    • What are the appropriate roles of industry, academia, and government organizations in the conduct of the research?
  • What mechanisms should be used to develop research goals and to ensure program focus?
  • How can intellectual property rights be shared among research performers/program sponsors?
  • How can program agility with respect to emerging research opportunities be maintained?
    • For example, can collaborative research be performed without the need to build and own a state-of-the-art fabrication facility?
    • How can management overhead costs be controlled and minimized?
  • What mechanisms should be put in place to enable transfer of knowledge and 'know-how' to the sponsors?
• How important is the production of highly-trained graduate students in a collaborative memory research program?

The remarkable progress in semiconductor memory technology has enabled an amazing array of consumer products. However, it is becoming increasingly clear that in information processing applications, especially those utilizing the multi-core processors, access to embedded memory is a key to achieving maximum performance. The trend to stacked processor/memory structures clearly indicates a need for substantial decreases in memory access times. While desirable attributes of memory devices are high speed, high density, long retention, and low-voltage operation, the device physics sets fundamental limits and trade-offs on our ability to integrate all desirable attributes into one memory element. In particular, what can be called "The Voltage-Time Dilemma" appears to characterize the limits of semiconductor memory scaling and performance. At the most basic level, for an arbitrary memory element, there is interdependence between operational voltage, the speed of operation and the retention time. This forum will examine the limits of scaling and performance for emerging semiconductor memories with an emphasis on embedded applications. Forum discussion will be centered around three major themes: 1) new memory devices, e.g. the "memristor", 2) memory architectures, and 3) technology platforms.

The invention of nonvolatile embedded memory with high speed and high density would imply a revolution in chip architectures, create new global applications, markets etc. As an example, 3D structures for embedded memory have recently demonstrated that in multicore applications, increased memory access bandwidth can negate the explosion in required memory. Ultimately these explorations could drive new computation models.